According Moore's law, the integration degree of a semiconductor device such as a transistor doubles every two years. Such an increase of the integration degree in semiconductor chips leads to micro-sized transistors and interconnections.
As the interconnections are fabricated in a micro-size, resistance R and capacitance C between interconnections increase, so that the RC delay time is lengthened. Such an increase of the RC delay time causes degradation of the operating speed and performance of the semiconductor device.
Accordingly the interconnections are metallized using copper, which has a resistance lower than that of aluminum.
Unlike aluminum metallization, copper metallization employs a process called a dual damascene process.
According to the dual damascene process, an insulating layer is formed with a via for connection with a lower conductive layer and a trench for an interconnection region. A barrier metal layer for preventing transfer of copper into the insulating layer is formed on inner walls of the via and the trench. Then, the via and trench are filled with copper.
Further, in order to reduce the capacitance between the interconnections, an interlayer dielectric layer including low-k materials, such as fluorinated silicate glass (FSG, k=3.7) or organosilicate glass (OSG, k=2.8), are used instead of silicon oxide (SiO2, k=4.2).
Furthermore, in order to further reduce the dielectric constant k of the dielectric material of the insulating layer, a porous low-k material is used, which has the dielectric constant (k=1) of vacuum by artificially forming pores in an ordinary low-k material.
However, because the porous low-k material has a lot of pores therein, a barrier metal used in the copper metallization penetrates into the pores. As a result, the dielectric constant of the porous low-k material is increased.
Hereinafter, a conventional method of forming a copper interconnection in a porous low-k thin film will be described with reference to the accompanying drawings.
Referring to FIG. 1A, a lower insulating layer 100 is formed on a semiconductor substrate (not shown) having semiconductor devices such as a transistor formed thereon. A first metal interconnection 101 is formed in the lower insulating layer 100 through a damascene process. An intermetallic insulating layer 102 is formed on the lower insulating layer 100 having the first metal interconnection 101 using a porous low-k material.
Then, referring to FIG. 1B, a via hole is formed in the intermetallic insulating layer 102 using a photoresist (PR) pattern (not shown) having a first opening corresponding to the first metal interconnection 101, and then the PR pattern is removed. A trench for forming a second metal interconnection is formed in the intermetallic insulating layer 102a, in which the via hole is formed, using another PR pattern (not shown) having a second opening larger than the first opening corresponding to the first metal interconnection 101.
Subsequently, referring to FIG. 1C, a barrier metal layer 103 and a conductive layer 104 are sequentially formed on the semiconductor substrate having the intermetallic insulating layer 102a in which the via hole and the trench are formed. Then, the barrier metal layer 103 and the conductive layer 104 are polished by a chemical mechanical polishing (CMP) process until the top surface of the intermetallic insulating layer 102a is exposed. Accordingly, the second metal interconnection is formed, and simultaneously a via for connecting the first and second metal interconnections is formed.
At this time, as illustrated in FIG. 2, because the intermetallic insulating layer 102a is formed of the porous low-k material having many pores, the material of the barrier metal layer 103 penetrates into the intermetallic insulating layer 102 through the pores.
Therefore, the dielectric constant of the intermetallic insulating layer 102a is increased. The increase of the dielectric constant leads to an increase of the capacitance C between the interconnections. As a result, this increases an RC delay time, and thereby reduces the operating speed and performance of the semiconductor device.